1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly to a liquid crystal display panel of line on glass (LOG) type and a fabricating method thereof that is adaptive for minimizing a line resistance of LOG-type patterns provided on the liquid crystal display panel.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) controls a light transmittance of a liquid crystal using an electric field to display a picture. To this end, the LCD includes a liquid crystal display panel having liquid crystal cells arranged in a matrix type, and a driving circuit for driving the liquid crystal display panel.
In the liquid crystal display panel, gate lines and data lines are arranged in such a manner to cross each other. The liquid crystal cell is positioned at each area where the gate lines cross the data lines. The liquid crystal display panel is provided with a pixel electrode and a common electrode for applying an electric field to each of the liquid crystal cells. Each pixel electrode is connected, via source and drain electrodes of a thin film transistor as a switching device, to any one of data lines. The gate electrode of the thin film transistor is connected to any one of the gate lines allowing a pixel voltage signal to be applied to the pixel electrodes for each one gate line.
The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for controlling the gate driver and the data driver, and a power supply for supplying various driving voltages used in the LCD. The timing controller controls a driving timing of the gate driver and the data driver and applies a pixel data signal to the data driver. The power supply generates driving voltages such as a common voltage Vcom, a gate high voltage Vgh and a gate low voltage Vgl, etc. The gate driver sequentially applies a scanning signal to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal display panel one line by one line. The data driver applies a data voltage signal to each of the data lines whenever the gate signal is applied to any one of the gate lines. Accordingly, the LCD controls a light transmittance by an electric field applied between the pixel electrode and the common electrode in accordance with the pixel voltage signal for each liquid crystal cell, to thereby display a picture.
The data driver and the gate driver directly connected to the liquid crystal display panel are integrated into a plurality of integrated circuits (ICs). Each of the data driver IC and the gate driver IC are mounted in a tape carrier package (TCP) to be connected to the liquid crystal display panel by a tape automated bonding (TAB) system, or mounted onto the liquid crystal display panel by a chip on glass (COG) system.
Herein, the driver ICs connected, via the TCP, to the liquid crystal display panel by the TAB system receives control signals and direct current voltage signals inputted from the exterior over signal lines mounted onto a printed circuit board (PCB) connected to the TCP, and are connected to each other. More specifically, the data driver ICs are connected, in series, via signal lines mounted onto the data PCB, to each other, and commonly receive control signals from the timing control signal, a pixel data signal and driving voltages from the power supply. The gate driver ICs are connected, in series, via signal lines mounted onto the gate PCB, and commonly receive control signals from the timing controller and driving voltages from the power supply.
The driver ICs mounted onto the liquid crystal display panel by the COG system are connected to each other by a line on glass (LOG) system in which signal lines are mounted on the liquid crystal display panel, that is, a lower glass, and receive control signals from the timing controller and the power supply and driving voltages.
Recently, even when the driver ICs are connected to the liquid crystal display panel by the TAB system, the LOG system is adopted to eliminate the PCB, thereby permitting the liquid crystal display to be manufactured into a thinner type. Particularly, signal lines connected to the gate driver ICs requiring relatively small signal lines are provided on the liquid crystal display panel by the LOG system to thereby eliminate the gate PCB. In other words, the gate driver ICs of TAB system are connected, in series, to each other over signal lines mounted onto the lower glass of the liquid crystal display panel, and commonly receive control signals and driving voltage signals, which are hereinafter referred to as “gate driving signals”.
For instance, as shown in FIG. 1, the liquid crystal display omitting the gate PCB by utilizing LOG-type signal wiring includes a liquid crystal display panel 1, a plurality of data TCPs 8 connected between the liquid crystal display panel 1 and a data PCB 12, a plurality of gate TCPs connected to other side of the liquid crystal display panel 1, data driver ICs 10 mounted in the data TCPs 8, and gate driver ICs mounted in the gate TCPs 14.
The liquid crystal display panel 1 includes a lower substrate 2 provided with various signal lines and a thin film transistor array, an upper substrate provided with a color filter array, and a liquid crystal injected between the lower substrate 2 and the upper substrate 4. Such a liquid crystal display panel 1 is provided with a picture display area 21 that consists of liquid crystal cells provided at crossings between gate lines 20 and data lines 18 for the purpose of displaying a picture. At the outer area of the lower substrate 2 located at the outer side of the picture display area 21, data pads are extended from the data lines 18 and gate pads are extended from the gate lines 20. Further, a LOG-type signal line group LOGG for transferring gate driving signals applied to the gate driver IC 16 is positioned at the outer area of the lower substrate 2.
The data TCP 8 is mounted with the data driver IC 10, and is provided with input pads 24 and output pads 25 electrically connected to the data driver IC 10. The input pads 243 of the data TCP 8 are electrically connected to the output pads of the data PCB 12 while the output pads 25 thereof are electrically connected to the data pads on the lower substrate 2. Particularly, the first data TCP 8 is further provided with a gate driving signal transmission group 22 electrically connected to the LOG-type signal line group LOGG on the lower substrate 2. This gate driving signal transmission group 22 applies gate driving signals from the timing controller and the power supply, via the data PCB 12, to the LOG-type signal line group LOGG.
The data driver ICs 10 convert digital pixel data signals into analog pixel voltage signals to apply them to the data lines 18 on the liquid crystal display panel.
Similarly, the gate TCP 14 is mounted with a gate driver IC 16, and is provided with a gate driving signal transmission line group 28 electrically connected to the gate driver IC 16 and output pads 30. The gate driving signal transmission line group 28 is electrically connected to the LOG-type signal line group LOGG on the lower substrate 2 while the output pads 30 are electrically connected to the gate pads on the lower substrate 2. As shown in FIG. 1, the LOG-type signal line group LOGG is connected between the first data TCP 8 and a first gate TCP 14 and between the adjacent gate TCPs 14.
Each gate driver IC 16 sequentially applies a scanning signal, that is, a gate high voltage signal Vgh to a gate line 20 in response to input control signals. Further, the gate driver IC 16 applies a gate low voltage signal Vgl to the gate line 20 in the remaining interval other than an interval supplied with the gate high voltage signal Vgh.
The LOG-type signal line group LOGG usually consists of signal lines for supplying direct current voltage signals such as a gate high voltage signal Vgh, a gate low voltage signal Vgl, a common voltage signal Vcom, a ground voltage signal GND and a supply voltage signal Vcc and gate control signals such as a gate start pulse GSP, a gate shift clock signal GSC and a gate enable signal GOE.
FIG. 2A is a plan view corresponding to a portion “A” between the first data TCP 8 and a first gate TCP 14 as a part of the LOG-type signal line group LOGG in FIG. 1 and FIG. 2B is a sectional view taken along the I-I′ line in FIG. 2A. As shown in FIGS. 2A and 2B, such LOG-type signal line group LOGG is arranged, in parallel, in a fine pattern at a very confined narrow space like a pad portion positioned of an outer area of a picture display part 21. The LOG-type signal line group LOGG includes a LOG-type signal line 26 supplying the gate low voltage VGL and other LOG-type signal lines 27 supplying the gate high voltage signal Vgh, the common voltage signal Vcom, the ground voltage signal GND, the supply voltage signal Vcc and a plurality gate control signals, respectively. The LOG-type signal line group LOGG is provided on the lower substrate 2, and a gate insulating film 34 and a protective film 36 are disposed on the LOG-type signal line group LOGG. The LOG-type signal line group LOGG is formed from a gate metal layer having a relatively large resistivity of about 0.046 Ω upon a forming process of the gate lines 20. Thus, the LOG-type signal line group LOGG has a larger resistance component than the signal lines formed from a copper film at an existing gate PCB. As a resistance value of the LOG-type signal line group LOGG is in proportion to a line length, its line resistance value is increased, as it becomes more distant from the data PCB 12, to thereby attenuate a gate driving signal. As a result, gate driving signals transferred over the LOG-type signal line group LOGG are distorted due to its line voltage value to cause a deterioration in a quality of a picture displayed on the picture display part 21.
More specifically, a voltage difference occurs from a gate driving signal applied for each gate driver IC 16 due to a line resistance value of the LOG-type signal line group LOGG. Since a line resistance value according to a length of the LOG-type signal line group LOGG is increased more as the LOG-type signal line group LOGG becomes more distant from the data PCB 12, a gate driving signal is attenuated. Due to a difference of gate driving signals applied for each gate driver IC 16, a cross-line phenomenon occurs between horizontal line blocks connected to different gate driver ICs at the picture display part 21, thereby causing a divided display of the field.
Particularly, this cross-line phenomenon between horizontal line blocks is caused by the fact that a gate low voltage Vgl of a plurality of gate driving signals is supplied differently for each gate driver TCP 14, that is, each gate driver IC 16 due to a line resistance of the LOG-type signal line group LOGG. A distortion of the gate low voltage Vgl in the gate driving signals supplied over the LOG-type signal line group LOGG greatly affects a picture quality of the picture display part 21. Herein, the gate low voltage Vgl allows a pixel voltage charged in the liquid crystal cell in a gate high voltage (Vgh) interval to be maintained until the next pixel voltage is charged. This is because the charged pixel voltage is varied when the gate low voltage Vgl is distorted.
In order to prevent an attenuation of a gate driving signal, particularly a gate low voltage caused by a line resistance of the LOG-type signal line group LOGG, the LOG-type signal line group LOGG must have a large sectional view or a small resistivity to thereby attenuate a resistance component.
However, since an outer area of the picture display part 21 provided with the LOG-type signal line group LOGG is confined, there exists a limit in enlarging a sectional area of the LOG-type signal line group LOGG. Also, since it is formed from a gate metal layer, there exists a limit in reducing a resistivity value of the LOG-type signal line group LOGG. Therefore, a scheme for reducing a line resistance of the LOG-type signal line group LOGG arranged in a fine pattern within the confined area is required.